| 1. | Many mcus use the harvard architecture , in which the program is kept in one section of memory usually the internal or external sram
很多mcu使用harvard体系，程序保存在内存的一段中（通常是内部的或外部的sram ） 。 |
| 2. | Adsp sharc21060 is one of current digital signal processing boards based on super harvard architecture , and it " s architecture is designed to streamy parallel
Adspsharc21060是一种基于超级哈佛结构的通用数字信号处理器， sharc的结构被设计为流水线并行处理器。 |
| 3. | Different from general microprocessors , dsps have harvard architecture or enhanced harvard architecture and units of dsps can work in parallel . to perform multiplication in high speed , dsps also include hardware multiplier in its cpu
与通用微处理器不同，数字信号处理器采用了哈佛总线结构或改进哈佛总线结构，具有高度的并行性，为了快速完成乘法计算在cpu中增设了硬件乘法单元。 |
| 4. | The risc mcu core is based on harvard architecture with 14 - bit instruction length and 8 - bit data length and two - level instruction pipeline the performance of the risc mcu has been improved by replacing micro - program with direct logic block
设计的riscmcu采用14位字长指令总线和8位字长数据总线分离的harvard结构和二级指令流水设计，并使用硬布线逻辑代替微程序控制，加快了微控制器的速度，提高了指令执行效率。 |
| 5. | Tms320vc5402 is a fixed - point digital signal processor , made by texas instruments incorporated , which is 16 - bit word length . vc5402 has enhanced harvard architecture built around one program bus , three data buses , and four address buses for increased performance and versatility
另外，采用mcs - 51系列cpu作为采集处理卡板载mcu也存在一些比较严重的问题，如cpu的指令执行速度慢，总线带宽窄等缺点，不能完成数据的高速处理。 |
| 6. | The core is based on harvard architecture with 16 - bit instruction length and 8 - bit data length . the performance of mcu has been improved greatly by introducing single - clock - cycle instructions , setting multiple high - speed working registers and replacing micro - program with direct logic block etc . to keep the mcu core reusable and transplantable , the whole mcu core has been coded for synthesis in verilog hdl
该mcu核采用哈佛结构、 16位指令字长和8位数据字长，通过设计单周期指令、在内部设置多个快速寄存器及采用硬布线逻辑代替微程序控制的方法，加快了微处理器的速度，提高了指令的执行效率。 |
| 7. | It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ) , 5 - stage pipeline , hardware multiplier and divider , interrupt controller , 16 - bit i / o port and a flexible memory controller . new modules can easily be added using the on - chip amba ahb / apb buses . it has flexible peripheral interfaces , so can be used as an independent processor in the board - level application or as a core in the asic design
它遵照ieee - 1745 （ sparcv8 ）的结构，针对嵌入式应用具有以下特点：采用分离的指令和数据cache （哈佛结构） ，五级流水，硬件乘法器和除法器，中断控制器， 16位的i / o端口和灵活的内存控制器，具有较强的异常处理功能，新模块可以轻松的通过片上的ambaahb / apb总线添加。 |
| 8. | On the base of analyzing the sparc instruction set , this paper researches the pipeline technology and the resolution of correlation problems , and these problems were resolved by using the harvard architecture , internal forwarding and delay branch technology
本文在分析sparc指令系统的基础上，研究了流水技术及其相关问题的解决方法，并通过在硬件上使用哈佛结构、提前写寄存器的操作时间以及内部前推和延迟转移等技术较好的解决了结构相关、数据相关和转移相关的问题。 |
